A Brief History of Reduced Instruction Set Computers
The core concepts that define RISC (Reduced Instruction Set Computer) processors first emerged in the 1940s from the work of pioneering computer scientist Alan Turing. In his seminal research on theoretical machine architectures, Turing explored the idea of a simplified computing engine that could operate efficiently with only a small number of basic instructions.
However, it took until the 1970s before the first RISC systems began development in universities and corporations. The term "RISC" itself was coined between 1980-1984 by David Patterson and his team at UC Berkeley, who created their own RISC processor as part of an experiment to increase computing performance.
At the same time, engineer John Cocke was leading an internal project at IBM to design a RISC-based microarchitecture to improve the speed of the company‘s telephone switch hardware. This system, the 801 prototype, used an innovative 24-bit RISC architecture. Cocke‘s work built upon earlier IBM research from the mid 1970s that also conceptually aligned with the RISC philosophy of simplifying processor design to boost efficiency.
The ideas refined in academia and industry R&D quickly moved into commercial products by the mid-1980s. Chuck Moore designed the first general-purpose RISC microprocessor, the Novix NC4016, based on concepts he researched in the 1970s. Berkeley‘s RISC research spawned the commercial SPARC architecture, originally released in 1987.
Other players like MIPS Computer Systems soon followed with their own RISC offerings. Within a few years, a majority of computing hardware vendors had changed over to adopting RISC principles in their processor designs to unlock significant performance gains.
This chart shows the dramatic increase in RISC adoption rates across all market segments that accelerated in the late 1980s:
1986 3% RISC adoption
1987 6% RISC adoption
1988 13% RISC adoption
1989 23% RISC adoption
1990 37% RISC adoptionData Source: Bajwa et al, "Instruction Set Architecture Trends and Implementation Issues"^[1]
Core Design Elements of RISC Processors
The foundational premise behind RISC processors is reducing complexity from both hardware and software to achieve design simplicity. The main techniques used include:
- Simpler Instructions – RISC instruction sets only include basic, fundamental operations that map efficiently to the underlying hardware implementation. These simplified instructions operate directly on register or memory operands.
- Fixed Instruction Formats – A key aspect is using fixed length instructions, commonly 32 bits or 64 bits long depending on the architecture. This consistency improves fetch performance and eases pipelining.
- Fewer Instruction Types – RISC ISAs have under 250 instructions total compared to over 800 or more for complex architectures like x86. Removing niche or specialized operations is a central element.
- Register-Based Operands – Instead of frequent memory access, RISC processors emphasize direct register operations for the bulk of processing. Larger register files with over 30 registers are common.
- Pipelined Execution – Throughput is boosted via instruction pipelines, which allow simultaneous fetch, decode, execute steps on separate instructions from a program.
- Branch Prediction – Dedicated hardware guesses the path of branch instructions to minimize pipeline stalls from control hazards.
Additional common RISC techniques like delayed branches, dynamic scheduling, register renaming/windows, and SIMD instructions provide further performance benefits once the base architecture is simplified.
The aggregate impact of these RISC design principles results in processors that require fewer overall transistors while achieving much higher clock speeds and instructions-per-clock efficiency versus complex instruction set computer (CISC) alternatives.
Modern RISC Architectures Power the Computing Industry
Since their breakout in the 1980s, RISC designs have evolved dramatically in performance and capability while retaining the central ethos of simplified instructions enabling optimized hardware behavior. Modern RISC architectures now serve as the foundation for the vast majority of new processor implementations across every computing segment.
Popular RISC instruction set architectures include:
ARM – Created for embedded systems, now the dominant processor architecture for mobile and IoT devices. Key properties include high efficiency, customizability, and licensing model.
MIPS – Pioneering 32-bit RISC ISA with a focus on fast, pipelined execution. Originally targeted workstations, still used widely in networking and embedded gear.
SPARC – Sun Microsystems‘ open RISC ISA that scales from embedded to supercomputers. Known for innovation in multi-threading and as a popular server CPU.
Power / PowerPC – RISC design co-developed by Apple, IBM, and Motorola during early 1990s for personal computers. Power evolved into a server/HPC architecture while PowerPC continues in embedded.
PA-RISC – Introduced by HP in mid-80s for Unix workstations and servers. Dropped in early 2000s for Intel‘s Itanium and x86 chips.
RISC-V – Modern open source ISA that has seen rapid recent growth for IoT, AI, and other applications. Takes inspiration from earlier RISC designs with a modular approach.
RISC architectures typically outpace CISC alternatives like x86 processors in raw speed at a given manufacturing process node. This performance advantage comes from both the simplified instructions as well as uniform pipelines that can be highly optimized in the hardware implementation.
Modern RISC processor performance continues climbing at a blazing pace according to leading benchmarks:
Processor Year Released SPECint Score
ARM Cortex-A72 2015 119
Oracle SPARC M7 2015 236
Fujitsu A64FX 2019 742
AWS Graviton2 2020 900+ (estimated)Data Source: SPEC CPU Benchmark Results, Spec.org^[2]
Contrasting RISC and CISC Design Philosophies
The key differences between RISC and CISC (complex instruction set computing) processor architectures include:
CISC
- Hardware flexibility for new instructions
- Code density via specialized instructions
- Emphasis on maximizing software compatibility
- Typically stronger legacy code support
RISC
- Software flexibility through simpler building blocks
- Hardware simplicity improves speed and power
- Streamlined pipeline for high single-thread performance
- Less legacy overhead enables optimization
The complex instruction set of CISC ISAs like x86 includes variable length encodings, operations working directly on memory instead of registers only, and instructions that require multiple cycles to complete. This provides extensive flexibility for developers to code algorithms in powerful ways that map well to the hardware paradigm.
However, these richer, more complex instructions incur penalties around performance, power efficiency, pipeline complexity and other fabric implementation costs.Extraneous hardware must support niche operations.
By contrast, RISC ISAs employ fixed length instructions encoded simply for rapid decoding. Most instructions operate on registers and complete in one cycle, easing pipelining with less control complexity. The lack of variable timing, simpler logic, and stripped down command set all contribute to much higher peak operating frequencies.
While the substantial software legacy burden has helped entrench CISC processors like Intel x86 chips in client computing, RISC adoption continues taking over the majority of volume server deployments as well as nearly all mobile and embedded use cases. Their efficiency, availability, and scalability have made RISC microarchitectures the gold standard for modern workloads.
References
[1] Bajwa et al, Instruction Set Architecture Trends and Implementation Issues. IEEE Computer, Jul 1997. [2] SPEC CPU2017 Benchmark Results. https://www.spec.org/cpu2017/results/